ASIC Design Engineer

About Black Sesame Technologies

Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533), Black Sesame Technologies is a leading AI SoC provider. Our mass-produced AI chips are already deployed in the Automotive and Robotics markets, delivering high-performance, automotive-grade compute solutions at scale. Join us to build the future of intelligent machines from the ground up.

Job Description: ASIC Design Engineer

In this role, you will be part of the core team designing our next-generation AI compute engines. You will go beyond high-level RTL, diving into the fundamental hardware constraints that make high-performance AI silicon possible. You will focus on optimizing high-speed data path logic while ensuring the design meets rigorous timing and power requirements.

Responsibilities

• RTL Design: Implement high-efficiency logic modules using SystemVerilog/Verilog,

focusing on AI-specific ALU and datapath components.

• STA & Timing: Analyze and fix timing violations (Setup/Hold) to ensure the design

closes at target frequencies.

• Low Power & PPA: Apply basic low-power techniques (e.g., Clock Gating) and analyze

their impact on PPA.

• Design Sign-off: Run Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain

Crossing) checks to ensure robust silicon behavior.

• Backend Collaboration: Work closely with the physical design team to understand and

resolve congestion and timing issues.

Basic Qualifications

• BS/MS in Electrical Engineering or Computer Engineering.

• Hardware Fundamentals: Deep understanding of CMOS logic, Setup/Hold time,

Skew/Jitter, and the impact of PVT (Process, Voltage, Temperature) corners.

• STA Knowledge: Familiar with the concept of Static Timing Analysis, including path

delays, false paths, and multi-cycle paths.

• HDL Proficiency: Strong coding skills in SystemVerilog/Verilog with an emphasis on

synthesizeable code and hardware-oriented thinking.

• Digital Architecture: Understanding of pipelining, stalling, and bypass logic in high-

performance datapaths.

• Scripting: Proficiency in Python, Shell, or TCL (essential for EDA tool interaction).

You would be a "Star Candidate" if you have:

• ASIC Flow Experience: Familiarity with the industry-standard ASIC design flow (from

RTL to GDSII).• ALU/Math Foundations: Knowledge of computer arithmetic (Fixed-point, IEEE-754)

and its hardware implementation.

• Advanced CDC: Experience handling complex asynchronous interfaces and

synchronization techniques.

• RISC-V Exposure: Understanding of RISC-V ISA and its pipeline stages.